Sineties

MOS SILICON GATE 2500 SERIES

METAL GATE 2000 AND 2400 SERIES

SECTION 1 2 3

TABLE OF CONTENTS

TITLE

Silicon Gate Technology

Designing with Silicon Gate; MOS/TTL Interface 2500 Series MOS Silicon Gate Specifications

2501 2502/2503/2504 2505/2512 2506/2507/2517

. 2508

2509/2510/2511 2513/2514

2516

2518/2519 2521/2522 2524/2525

Fully Decoded, 256X1 Static Random Access Memory 1024-Bit Capacity Multiplexed Dynamic Shift Registers 512 and 1024 Bit Recirculating Dynamic Shift Registers Dual 100-Bit Dynamic Shift Registers

Fully Decoded, 1024X1 Dynamic Random Access Memory Tri-State Output, Dual 50-100-200 Bit Static Shift Registers High-Speed 64X7X5 Character Generator, 512X5 Static Read-Only Memory

High-Speed 64X6X8 Static Character Generator

Hex 32-Hex 40-Bit Static Shift Registers

Dual 128-132 Bit Static Shift Registers

512 and 1024 Bit Recirculating Dynamic Shift Registers

2000/2400 Metal Gate MOS Specifications

2001 2002 2003 2004 2005 2010 2400 Series

Dual 16-Bit Static Shift Register

Dual 25-Bit Static Shift Register

Dual 32-Bit Static Shift Register

Dual 50-Bit Static Shift Register

Dual 100-Bit Static Shift Register

Dual 100-Bit Static Shift Register DC to 3 MHz

Fully Decoded 1024 and 2048-Bit Static Read-Only Memori

MOS SURE 883 Program

MOS/ROM Programming Software Information

2400 Series Static Read-Only Memories

2513 Static Character Generator and 2514 Static Read-Only Memory 2516 Static Character Generator

Linear and Digital Product Information Linear Product Line (Bipolar) Digital Product Line (Bipolar)

Signetics Sales Offices

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101 103 103 103 103 103 107 es 111

119

125 127 139 151

163 165 166

169

25% to 50% recycled paper

Copyright 1971

SIGNETICS CORPORATION

IMPORTANT NOTICE

This handbook contains information on new products recently announced. Although believed to be accurate, this preliminary data is subject to change without notice.

Signetics Corp. cannot assume responsibility for any circuits shown or represent that they are free from patent infringement.

SECTION

SILICON GATE TECHNOLOGY

SILICON GATE TECHNOLOGY

WHY SILICON GATE TECHNOLOGY?

INTRODUCTION

There are many MOS processes available today, ranging from high threshold, 1-1-1 orientation silicon, P-MOSTs to the less common dielectrically isolated, complementary MOS, ion implanted, silicon nitride, and silicon gate monolithic circuit. The problems which arise for MOS manufacturers and users can be summarized many times as one question: Which technology?

In this section, a brief comparison of the available MOS technologies is made. This is followed by a description of the

P Channel 1-1-1 Crystal, Metal Gate 1-0-0 Crystal, Metal Gate Nitride Silicon Gate, (111) Crystal lon Impl. (Metal Gate) Low Threshold Approach Self Aligned Gate N Channel

Complementary

SILICON GATE PROCESS FABRICATION SEQUENCE

Basic process flow is illustrated in Figure 2. Using this chart as a guide, the process can be described as follows.

STEPA

The wafers are thoroughly inspected, cleaned, oxidized and masked to delineate the area where the drain, source and channel will eventually be formed. The gate dielectric is then grown. Both the initial oxide and the gate dielectric can be grown in any manner, to any de- sired thickness, without affecting junction character- istics. The initial oxide thickness is normally chosen to

PROCESS RANKING

silicon gate process flow sequence and a comparison of its advantages and disadvantages.

MOS TECHNOLOGIES

The numbers of MOS technologies available are numerous and each has its cwn advantages and disadvantages. Figure 1 shows a process ranking for some of the major technologies now available. The processes are weighted on five different factors: speed, chip area, power dissipation, bipolar compat- ibility and cost. The Silicon Gate Process which ranks highest forms the basis for the 2500 Series.

COMPATIBILITY | COST

FIGURE 1.

minimize poly-to-substrate capacitance, maximize poly-to-substrate parasitic field turn-on voltage and thin enough to minimize the step over which metal lines may eventually have to travel.

STEP B

The poly-crystalline silicon is deposited, a masking oxide is formed and the sandwich is then masked and etched to delineate the gate structure and the drain- source beds. The quality, cleanliness and thickness uniformity of the deposited poly is important. Also delineating the poly-crystalline lines is a critical step, since some of these lines determine the channel length of the completed MOS transistors.

SILICON GATE TECHNOLOGY

STEP C STEP E

Boron is deposited to dope the poly-crystalline silicon Contacts are opened and metallization is deposited, and to form the Pt beds for source and drain. The delineated and sintered. The metallization is fairly doping of the poly lines and P* beds is straightforward standard. As with the metal gate processes which and virtually any clean source of boron can be used. may have high oxide steps, care must be taken with Because the pre-deposited poly-silicon gate is used to the silicon gate process to minimize the height of the mask the boron diffusion, the gate,source and drain are steps over which metal must travel in order to mi automatically self aligned. imize metal microcracking problem

STEP D A multi-layered protective glass is deposited over the A clean layer of oxide is deposited over the entire finished structure and holes are opened to the bonding wafer to passivate the P+ beds and provide isolation pads to give the final cross-section shown in Figure 3. between poly-silicon and metal lines. Deposition of Glass passivation is mandatory, even with the silicon the passivating oxide requires strict control over the gate process, to protect the aluminum metalization cleanliness of the deposition system to minimize oxide from mechanical abrasion and particulate contamina- defects and contamination. tion.

SILICON GATE PROCESS FLOW

| om =m eae = ee him

Y-CRYSTALLINE SILICON DEPOSITION

oa HELL

STEP C: P+ BED DOPING

STEP E: ALUMINUM METALIZATION PATTERN

i

|

ai |

FIGURE 2.

FINAL DEVICE CROSS SECTION

4a Saint se

FIGURE 3.

SILICON GATE TECHNOLOGY

ADVANTAGES AND DISADVANTAGES OF SILICON GATE

The silicon gate process has a number of advantages which make it attractive for the production of complex, high density circuits. Before expanding on these advantages, we will first explore two of the more prominent disadvantages of the process:

Ratio Versus Ratioless

Because of the self-aligned gate feature, the parasitic drain-to-source capacitance is small. In designing dy- namic shift registers, it is advantageous to design ‘‘ratio- less’ devices where parasitic capacitance is used to momentarily store charge. Using silicon gate, a ratio- less type design is not feasible, so the more area con- suming ratio type must be used. However, the silicon gate ratio design is competitive in size with the metal gate ratioless version, since area is saved by the smaller gate area (no need for alignment tolerance allowance), plus the use of the poly-silicon as a interconnecting layer.

Additional Depositions

Silicon gate processing requires more deposition steps than is required by standard metal gate processes. However, these processes can be easily controlled using modern, automated deposition equipment and built- in process control monitors.

The potential disadvantages of the silicon gate process are outweighted by the following advantages. Low Threshold Voltage Doped poly-silicon, used in place of the usual alu- minum gate electrode, yields threshold voltages typ- ically around -2.0 volts. This low threshold voltage is obtained using 1-1-1 orientation silicon, so the corre- sponding parasitic field turn-on voltage is still very high. High Gain The gain of the silicon gate device is high since 1-1-1 orientation is used as the starting material. Gain is typ- ically higher than low threshold voltage devices fabri- cated on 1-0-0 silicon because of higher carrier mobil- ity. Low Power The silicon gate device dissipates less power:

(1) Because of its low threshold it operates with lower power supply voltages.

(2) Its self-aligned gate essentially eliminates over- lap of the gate over the drain, so the capacitive load on the clock drive is less.

High Speed

High speeds are obtained because of low threshold voltages, high gain and low gate capacitance. Minimum Area

The poly-crystalline silicon layer provides yet another “half-layer’’ of interconnection. We call it a “‘half-

layer’’ since the crossing of poly-silicon over Pt beds is not allowed. Shallow junctions allow close Pt bed spacings and the self-aligned gate feature means no mask alignment tolerances are needed to register the gate to the Pt beds. In addition, direct contact of poly-to-substrate allows further area reduction.

To illustrate the size advantages, consider Figure 4. The 2005 and 2510 are both dual 100-bit static shift registers. However, the silicon gate 2510 is 15 percent smaller than its metal gate equivalent. Not only is it smaller but it has additional functions such as recir- culate logic, tri-state outputs, TTL compatibility and an on-chip clock generator. The silicon gate 2511 Dual 200-Bit Static Shift Register, offers twice the number of bits as the metal gate 2005 plus four ad- ditional functions in only 36 percent more area.

SIZE COMPARISON OF DICE

PART

Dual 100 Bit S.S.R. 12

; |

2005 (Metal Gate) 8,190mi Dual 100 Bit S.S.R.

(Silicon Gate)

Dual 200 Bit S.S.R. (Silicon Gate)

6,970mil2

FIGURE 4.

High Yield

The process of forming the gate oxide at the first stage of wafer fabrication and coating with a protec- tive layer of silicon inherently gives higher yields. In addition, the ability to compact a given circuit function into a smaller area gives a lower probability that a processing defect will occur on a die. This is especially true since the decrease in area does not come at the expense of masking tolerances. The higher yields result in lower costs.

Process Flexibility

The silicon process gate is compatible with other MOS technologies. lon implantation can be used to adjust thresholds and/or minimize gate-to-drain capacitance. Gate dielectrics can easily be changed without affecting junction characteristics, and C-MOST and N-MOST can easily be adapted to silicon gate processing.

Low Cost Packaging

Because the gate dielectric is protected by poly-silicon and the overlying layers of oxides, it is possible to reliably package silicon gate devices in silicone pack- ages. Cross-sections of metal gate and silicon gate devices are shown in Figure 5, The metal gate devices are protected by two layers: aluminum metallization and glass passivation. On the other hand, the silicon gate device is protected by four layers: (1) thick poly-

SILICON GATE TECHNOLOGY

LOW COST PACKAGING (Cont'd) The silicon gate process is a technology whichgives all of the . advantages needed to fabricate the next generation of cir- crystalline silicon (impervious to most harmful con- cuits: high packing density, high speed, low power and low taminants). (2) thick clean oxide, (3) a passivated di- cost. Because of these characteristics, silicon gate MOS tech- electric which also serves as a sodium barrier and, (4) nology has become an industry standard for state-of-the-art

a multi-layered protective glass. MOS LSI designs.

METAL GATE PROCESS

ata ponent GLASS PASSIVATION tl ea nn. Le

N-TYPE SILICON SUBSTRATE

Aint

————— ——— SSS —>_>__Z=

SIGNETICS SILICON GATE PROCESS

Then

SiNOtics

SECTION DESIGNING WITH SILICON GATE

MOS/TTL INTERFACE

10

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

DESIGNING WITH SILICON GATE

INTRODUCTION

Large scale, bipolar compatible MOS integrated circuits are now available to the systems designer because of the unique benefits of Signetics’ Silicon Gate Technology. Using com- plex MOS functions to form major systems blocks, joined and controlled by today’s wide variety of low cost TTL and DTL MSI and SSI functions, economical state-of-the-art systems are being produced with ease and efficiency.

THE SILICON GATE MOS BIPOLAR COMBINATION

Silicon Gate MOS - Bipolar designs offer the best of both worlds. MOS designs are most efficient when providing large, medium-speed arrays of identical cells, such as required for long serial shift registers, large Random Access Memories (RAMs) and large Read-Only-Memories (ROMs).

Bipolar designs are most efficient when providing high-speed connective logic functions (gates), small parallel registers, and small specialized logic combinations such as adders, com- parators, counters, decoders, and power drivers.

MOS-BIPOLAR COMPATIBILITY

Today’s systems are designed to utilize the benefits of both MOS and bipolar technology for maximum performance at minimum cost. Signetics recognizes the benefits of direct MOS-Bipolar interfacing and has created the Silicon Gate 2500 Series MOS with the express purpose of providing MOS density and bipolar compatibility.

INPUT INTERFACE

All 2500 series devices are manufactured with the P-channel enhancement mode silicon gate process. A typical data input structure is shown in Figure 1.

OUTPUT

FIGURE 1

The input transistor exhibits the transfer curve shown in Figure 2. The device is fully OFF at -1.8 volts or less (Vgs) and fully ON at -3.5 volts or more. To simplify the inter- facing of TTL and 2500 Series devices, the source voltage for the input transistor is specified at +5.0 volts. In practice, this point is tied to the +5.0 volt TTL Vcc supply. The re- quired MOS input levels are then specified as positive levels referenced to the TTL ground.

11

Series 2500 Input Thresholds “0” Input Voltage = Viz =+1.05 maximum@

Vcc = 5V “1"" Input Voltage = Vip = +3.2V minimum @ Vec = 5V

The input levels are specified assuming Vcc is exactly +5.0V. The allowable Vcc tolerance is +5%, however any variation in actual Vcc will be tracked directly by the input threshold point.

Example (a): +5% Vcc @ Vcc= +5.25V ViL = 1.3V max. Vin = +3.45V minimum

Example (b): -5% Vcc @Vcc = +4.75V Vit = 0.8V max. Vin = +2.95V minimum

2 mi ° 2 - 3 >

Vigs (VOLTS) FIGURE 2 In actual practice, tying the TTL Vac to the MOS Vcc

will ensure maximum noise margin since the TTL output levels and MOS input thresholds will track.

54/7400 TTL

Figure 3(a) and (b) show a typical 7400 Series gate circuit and transfer characteristic.

FIGURE 3(a)

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

54/7400 TTL

Vec =5V + 5%

uw @ ro mr) co) > 2 3

* EXTERNAL 10K PULL-UP RESISTOR

FIGURE 4

INPUT VOLTAGE

8000 TTL

Figure 5 illustrates a typical 8800 series output structure.

FIGURE 3(b)

The output structure shown in Figure3(a) is normally specified as follows:

@ Voc = t5V +5% VoL = +0.4V maximum @ 16 mA sink VOH = +2.4V minimum @ 400 yA source

MOS devices require only negligible D.C. input current (ap- proximately 1A), so the current available from the TTL output is of no interest for steady state conditions. Vo, _ is perfectly compatible with the MOS offering at least 400mV of noise margin in the O state. Voy however, is not suffi- cient to guarantee a 1 level to the MOS input since the TTL VOM allows a Vec - Voy separation of as much as 2.85V

Voc = 5.25V, Voy = +2.4V; 5.25V - 2.4V = 2.85V). chasis Assuming a common Vcc, this results in a virtual Voy The 8800 series circuit typically offers an unloaded output of 2.15V, far too low for MOS. In practice, the TTL Voy voltage separated from Vcc by one Vpgo. Therefore the out- will track Vcc, rather than the opposite case just noted. put level driving MOS will always be approximately 0.75V Also Voy will be higher than +2.4 at 1uA IE. However, higher than the preceeding example for 7400 series circuits the TTL circuit is tested and guaranteed as in the example. resulting in at least 550mV 1 level noise margin under any conditions. Noise margin at 0 level is 400 mV, the same as The 7400 TTL output structure will typically provide a in the case of 7400 TTL. VOH approximately 1.5V (two Vie drops) below Vcc. When the MOS and TTL Vcc are tied, a 300mV noise Signetics guarantees 8000 Series TTL (See figure 6) VOH at margin (1.8V - 1.5V = 0.3V) is obtained. If Vcc is not tied 3.6V @ 10uA. Under worst case conditions, this results in common, the worst case typical noise margin is a negative a minimum guaranteed 0 level noise margin of 400mV for 200mV. In other words, a satisfactory 1 input level cannot tied Vcc. If the MOS and TTL Vcc are not tied (may vary be assured, even under typical conditions. independently), worst case guaranteed noise margin is

-150mV. This configuration requires a pull-up resistor. TO ASSURE A SATISFACTORY 1 OUTPUT LEVEL

FROM SERIES 7400 IN DRIVING SERIES 2500 MOS, AN WHEN Vc¢c’S ARE TIED COMMON, SERIES 8000 TTL EXTERNAL PULL-UP RESISTOR SHOULD BE CON- IN FIGURE 6 WILL INTERFACE DIRECTLY WITH NECTED FROM THE OUTPUT TO Vcc AS SHOWN IN SERIES 2500 MOS, WITHOUT THE NEED FOR AN Ex- FIGURE 4. . TERNAL PULL-UP RESISTOR.

12

DESIGNING WITH SILICON GATE # MOS/TTL INTERFACE

GATES FLIP-FLOPS

8808 Single 8-Input NAND Gate

8815 Dual 4-Input NOR Gate

8816 Dual 4-Input NAND Gate Dual Master-Slave J-K Binary 8840 Dual Expandable AND-OR-INVERT Gate Dual Master-Slave J-K Binary

8848 Expandable AND-OR-INVERT Gate Dual Master-Slave J-K Binary 8870 ‘Triple 3-Input NAND Gate DC Clocked J-K Binary 8875 Triple 3-input NOR Gate Dual J-K Binary 8880 Quad 2-Input NAND Gate Dual J-K Binary 8885 Quad 2-Input NOR Gate High Speed J-K Binary “See Note Below FIGURE 6

*For devices not listed,addan external pull-up resistor as in the 7400 example(Fig. 4).

DTL/UTILOGIC ® those noted for Series 800 circuits.

ree ; ; ; WHEN Vcc’S ARE COMMON, SERIES 2500 MOS MAY Logic forms utilizing an internal passive pull-up iesistat BE DIRECTLY DRIVEN BY SERIES 600 DTL AND (such .as DTL) will interface directly with 2500 Series MOS. SERIES 300 UTILOGIC CIRCUITS WITHOUT THE NEED Utilogic is guaranteed to provide output levels equivalent to FOR AN EXTERNAL PULL-UP RESISTOR.

2500 SERIES MOS-TTL INPUT CONSIDERATIONS (TTL Level data and clock inputs)

WORST CASE WORST CASE GUAR. GUAR. 1 LEVEL O LEVEL NOISE MARGIN NOISE MARGIN

EXTERNAL DRIVING DEVICE PULL-UP

RESISTOR (6)

Common Vcc 8000(1) Series TTL not req. 8000(2) Series TTL 10K 7400 Series TTL 10K 600 Series DTL (3) not req. 600 Series DTL (4) not req. 300 Series Utilogic (3) not req 300 Series Utilogic (4) not req.

Independent Vcc

All TTL 10K 400 600 Series DTL (3) not req, 150 (5) 600 Series DTL (4) not req. 150 (5) 300 Series Utilogic 10K (7) 150 (5) NOTES: FIGURE 7 (1) From List in Figure 6

(2) Not listed in Figure 6

(3) Passive Pull-up (resistor), 10% power supply

(4) Active Pull-up, +10% power supply

(5) Use +5% DTL or Utilogic power supply to maintain 400 mV noise margin

(6) From driving output to Voc (7) Certain Series 300 devices utilize a passive pull-up and require no external pull-up.

13

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

OUTPUT INTERFACE

TTL/DTL INPUT STRUCTURES

Standard TTL circuits employ the input structure shown in Figure 8.

TYPICAL TTL INPUT STRUCTURE

CLAMP OR SUBSTRATE DIODE

= GND

FIGURE 8

DTL circuits employ the structure shown in Figure 9.

TYPICAL DTL INPUT STRUCTURE

FIGURE 9

2500 SERIES OUTPUT STRUCTURES

Four basic types of output structures are used in the 2500 series: 1. Bare drain

2. Internal resistor pull-down 3. Push-pull 4. Three-state

See Figure 10. TYPICAL 2500 SERIES OUTPUT CIRCUITS

+Vcc +Vcc +Voc

of

Vpp

(A) BARE DRAIN (B) RESISTOR PULL-DOWN (C) PUSH-PULL

FIGURE 10

14

BARE DRAIN:

The bare drain output is the simplest structure and requires an external pull-down resistor. Bare drain is used where several outputs are to be tied together in a WIRED-OR configuration as shown in Figure 11.

WIRED-OR CONFIGURATION OF TWO BARE DRAIN DEVICES

OTL/TTL

O $V (Vpp)

FIGURE 11

The external resistor is chosen to sink the 1.6mA required by a TTL gate. In Figure 11, a 3.3K resistor is tied to the Vpp supply. The output voltage will be +0.4V or less de- pending on the actual Io, of the TTL input.

When the bare drain device is ON, it represents approx- imately 500 ohms. For the circuit of Figure 9, Voy is ap- proximately +3.7V more than sufficient to drive a TTL or DTL gate. Bare drain 2500 devices are listed in Figure 12.

BARE DRAIN SERIES 2500 DEVICES

FIGURE 12

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

RESISTOR PULL-DOWN

The second type of output has a pull-down resistor on the chip. The 2507 and 2517 are examples of this. The 2517 has a 20K ohm internal resistor for interfacing with MOS.

Resistor pull-down series 2500 devices are listed in Figure 13. The 2507 hasa7.5Kohm resistor, and if used in the WIRED- OR configuration with another 2507 output, will drive TTL directly as shown in Figure 14.

RESISTOR PULL-DOWN SERIES 2500 DEVICES

2507 7.5K

2517 = 20K

FIGURE 13

PARALLEL CONFIGURATION FOR 2507's

OTL/TTL

FIGURE 14

PUSH-PULL

The third type of output structure used in the 2500 Series is the push-pull circuit shown in Figure 10c. In the push-pull configuration, the gates of the two output devices are driven from complementary signals such that only one device is ON at atime. When the upper device is ON, the output is tied to Vcc through approximately 500 ohms. When the lower device in ON, the output is tied to Vpp through 500 ohms.

6

The advantage of this circuit is that no additional power is dissipated in either state. Both states have low impedance to the power supplies. Push-Pull output series 2500 devices are listed in Figure 15.

PUSH-PULL OUTPUT SERIES 2500 DEVICES

2521 2522

FIGURE 15

THREE-STATE

A disadvantage of the push-pull circuit is that paralleling of the outputs is not possible because two low impedance devices would be ON simultaneously directly across the power supplies. To avoid this condition, a three-state out- put is used. The third state is an open output configuration where both devices are OFF and is accomplished by using an OUTPUT ENABLE line tied to the gates of both output devices as shown in Figure 16. Three-state series 2500 devices are listed in Figure 17. |

DTL/TTL

OUTPUT ENABLE

FIGURE 16

THREE-STATE SERIES 2500 DEVICES

2510 2513

2511 2514

FIGURE 17

Figure 18 summarizes the output configurations used on the 2500 Series circuits.

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

OUTPUT CONSIDERATIONS FOR 2500 LINE

PRODUCT

NUMBER

2501 2502 2503 2504

2505/2524

2506 2507 2508 2509 2510 2511

2512/2525

2513 2514 2516 2517

DESCRIPTION

256 x 1 Static RAM

256 x 4 Dynamic Shift Register 512 x 2 Dynamic Shift Register 1024 x 1 Dynamic Shift Register 512 x 1 Dynamic Shift Register 100 x 2 Dynamic Shift Register 100 x 2 Dynamic Shift Register 1024 x 1 Dynamic RAM

50 x 2 Static Shift Register

100 x 2 Static Shift Register

200 x 2 Static Shift Register 1024 x 1 Dynamic Shift Register 64 x 7 x 5 Character Generator 512 x 5 ROM

64 x 6 x 8 Character Generator 100 x 2 Dynamic Shift Register

OUTPUT STRUCTURE.

3-State

Bare Drain Bare Drain Bare Drain Bare Drain Bare Drain 7.5K Resistor Bare Drain 3-State 3-State 3-State

Bare Drain 3-State 3-State 3-State

20K Resistor

TO DRIVE ONE TTL/DTL USE*

Direct 3.0K 3.0K 3.0K 3.0K 3.0K 6.8K 6.8K Direct Direct Direct 3.0K Direct Direct Direct 3.3K

2518 32 x 6 Static Shift Register 2519 40 x 6 Static Shift Register

2521. 128 x 2 Static Shift Register 2522 132 x 2 Static Shift Register

Bare Drain 6.8K Bare Drain 6.8K Push~Pull Direct Push-Pull Direct

“NOTE: Values are given for the maximum value of pull-down resistor ,output to Vopb-

FIGURE 18

“OR” TYING OUTPUTS

The characteristics of the four types of output structures differ when tied together. A basic feature of MOS is that the design limitation on output ““OR"’ing is related to the output voltage levels required and the RC time constant of the resulting network.

BARE DRAIN

The number of bare drain devices which can be tied together is limited by the output time constant and the Voy level required.

Switching time for the pull-down condition is determined by the load resistor Rpp and load capacitance C; . The MOS pull-up device is turned off and does not contribute to the negative going time constant. See Figure 19.

Cy_ is comprised of wiring capacitance (Cy) and output capacitance (COyT) from each of the paralleled outputs.

As the number of paralleled devices increases, the value of Rpp must be decreased to maintain speed.

When driving loads having significant input capacitance, Cy should be increased accordingly.

16

-"- |

° Cc 4

cr 7

| |

I I

wk aki Te Te, | | + +

FIGURE 19

As Rpp is decreased, Voy decreases since the impedance of Q1 when ON (approx. 500 ohms) will ratio with Rpp to pro- duce Voy: If Rpp is reduced too far, the output voltage will be insufficient to turn off the TTL gate being driven.

Figure 20 gives the recommended value of Rpp as a_func- tion of fan-out for 2500 series bare drain devices.

DESIGNING WITH SILICON GATE # MOS/TTL INTERFACE

FIGURE 20

* For te= 50ns

Figure 20 assumes 10pF of wiring capacitance and 5pF per output. It should be noted that when the MOS device is OFF, the TTL input current of 1.6mA is sunk to -5V. When set up for a fanout of 5, the 1.6mA from the TTL gate will bring the output to only -2.7V. In actuality the input clamp or substrate diode of the TTL gate will turn on and clamp the output to -1.0V. The diode will supply the additional current (approximately 1.9mA).

INTERNAL PULL-DOWN

When 2500 Series devices with internal pull-down resistors are paralleled, the equivalent resistance Rpp is the parallel combination of all the internal resistors. A chart of the equivalent resistance, output time constant and Voy for the 2507 with a 7.5K internal pull-down resistor is shown in Figure 21.

FIGURE 21

PUSH-PULL OUTPUTS

Push-Pull outputs allow low rise and fall times but cannot be paralleled because it would then be possible to have both a push and a pull device on at the same time resulting ina low impedance between the power supplies (and indeter- minate output level).

THREE STATE OUTPUTS

The three state output is designed to take advantage of push pull drive capability plus the ability to OR the outputs.

The third (or open) state is used when the chip is unselected. The selected output is free to drive the load without being affected by the other outputs tied to the bus.

Output rise and fall times for the WIRED OR configuration of three-state devices is a function of the ON resistance of the individual pull-up and pull-down devices together with the load capacitance.

17

A CLOCK DRIVER FOR 2500 SERIES MOS

In order to obtain optimum performance from MOS de- vices, they must be provided with clock signals of the proper amplitude, shape and timing. This section will present a simple clock generator and driver scheme suitable for use with 2500 Series MOS devices.

NOTE: The following devices employ on-chip clock gen erators and may be driven directly by TTL gates:

2509 2510 2511 2518 2519 2521 2522

The clock driver must provide relatively large voltage swings for the clock lines. In the case of 2500 Series MOS, the clock signal must swing from +5V to -12V. And it must providea clean waveform having reasonable rise and fall times (under 40 ns.) and lack of positive overshoot.

IMPROPER CLOCK WAVEFORMS

Some common examples of improper clocking are shown in Figures 23, 24, and 25.

IDEAL CLOCK WAVEFORM NOTE: . An ideal clock driving waveform.

FIGURE 22

POSITIVE OVERSHOOT NOTE: . Shows an overshoot occurring on the positive going transition of clock. This has the effect of forward biasing the substrate diode and must be avoided to prevent erratic behavior in the driven device.

FIGURE 23

INSUFFICIENT POSITIVE LEVEL NOTE: Shows the clock never returns to 5V (0 reference) to turn the input device OFF. This clock can sometimes appear to be functional. Data may toggle through a shift register, but will not be stored.

FIGURE 24

CROSS- COUPLED CLOCKS NOTE: Shows cross-coupling between two clock drivers usually caused by lack of clamping or non-active (high-impedance) switching in the positive direction.

FIGURE 25

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

The positive overshoots illustrated in Figure 23 and Figure 25 are the most common sources of clock driving trouble. When the clock line goes positive relative to the circuit substrate (Vcc) by more than approximately 0.3V, the substrate diode may become forward biased. When this occurs, device opera- tion may become erratic. And because the forward character- istics of the substrate diode may be different for different processing techniques, a clock driver may work properly with one device but not with another.

A properly designed driver utilizing level clamping will pre vent the overshoot problem.

THE DRIVER OUTPUT STRUCTURE

Figures 26, 27, and 28 show possible output driver struc- tures togéther with their advantages and disadvantages.

RESISTOR PULL-UP, POOR NOISE IMMUNITY, AND SLOW RISE TIME

FIGURE 26

PUSH-PULL, SLOW RISE AND FALL TIME

ie

12. (ACCEPTABLE) FIGURE 27

COMPLEMENTARY, EXCELLENT NOISE IMMUNITY, FAST RISE AND FALL TIME

ut

12. (BEST) FIGURE 28

18

The driver circuit recommended here (Figure 29) utilizes a complementary output structure to obtain maximum noise immunity and fast rise and fall time under heavy capacitive load. It is capacitively coupled to the TTL clock generator. Resistor Rq is required only when operating at a clock frequency of lower than 750 KHz. This resistor shifts the response of the driver input circuit toward the lower fre- quencies by lengthening the input time constant. One clock driver is required for each clock phase.

NOTES: Q,4, Qg 2N2222, Heat Sink Required

Qo, Q3 2N2905, Heat Sink Required Cy, Co 100pF

D,, 02° 1N914

Ry. Ro. Rg 330hms

Ra 2.2K (Required onty for operation below 750K Hz)

(FROM TTL)

FIGURE 29

GENERATING MULTIPLE PHASES

The 2500 Series MOS devices which require high level clocks also require more than one phase. The dynamic shift regis- ters require two phases and the 2508 dynamic RAM requires four phases.

TWO PHASE SYSTEM

The clock generator in Figure 30 produces alternate pulses - the width of which are one quarter of the input clock period (assuming a square wave clock). See Figure 32.

TWO PHASE TTL CLOCK GENERATOR

Vec

SYSTEM CLOCK

U DISABLE

FIGURE 30

When required, the clock pulse widths can be varied by using one-shot multivibrators such as the 8162 or 74121. Each phase width can be varied independently (the limiting factor being the clock period), see Figure 31(a), or a single one- shot ahead of the clock generator will change both phases simultaneously. See Figure 31(b) .

SiNGTiCS ERRATA- MOS HANDBOOK

Figure 29, Page 18— The correct Clock Driver Circuit is shown below.

R4 SIN (FROM TTL)

Q4, Qqg 2N2905, Heat Sink Required

Q9, Q3 2N2222, Heat Sink Required

C4, Co 100pF

Dj, Dg 1N914

R4, Ro, R3 33 Ohm

Rg 2.2K Ohm (Required only for operation below 750KHz)

DESIGNING WITH SILICON GATE ® MOS/TTL INTERFACE

METHOD OF PROVIDING INDEPENDENTLY VARIABLE CLOCK PHASES

TWO PHASE CLOCK GENERATOR WAVEFORMS

TWO PHASE CLOCK CLOCK OSCILLATOR GENERATOR

FIGURE 31(a)

METHOD OF PROVIDING VARIABLE CLOCK PHASES

TWO PHASE CLOCK ONE SHOT verore OSCILLATOR MV GENERATOR

FIGURE 31(b) FIGURE 32

FOUR PHASE SYSTEM The circuit shown in Figure 33(a) and (b) can be used to generate four phase clock signals for the 2508 1024 RAM.

DIVIDE-BY-12 SYNCHRONOUS COUNTER

CLOCK IN

(25 MHz)

FIGURE 33(a)

19

DESIGNING WITH SILICON GATE MOS/TTL INTERFACE

FOUR PHASE SYSTEM

FOUR PHASE DECODER

480ns e- 80ns

Pa (gj eS oa

FIGURE 33(b)

Figure 34 shows typical clock input capacitances for 2500 Series devices. The number of similar devices which can be driven by one clock driver is indicated.

DEVICE ee DRIVEN (INCLUDES CAPACITANCE (oF) ALLOWANCE FOR WIRING CAPACITANCE)

<2MHz (1) 2-4MHz (2)

(1) Drive capacity 1200pF

(2) Drive capacity 750pF

FIGURE 34

SiNCtiES -

21

SECTION

2500 SERIES MOS SILICON GATE. SPECIFICATIONS

3

22

Siotics

FULLY DECODED, 256 X1 STATIC RANDOM ACCESS MEMORY

2901

DESCRIPTION

The Signetics 2500 Series 256 x 1 Random Access Memory employs enhancement mode P-channel MOS devices inte- grated on a single monolithic chip. It is fully decoded, per- mitting the use of a 16-pin dual in-line package. Complete static operation requires no clocking.

FEATURES

@e FULLY DECODED ADDRESS

@ ACCESS TIME 1.0us GUARANTEED

@ POWER DISSIPATION -1.6mW/BIT MAXIMUM DURING ACCESS

e STANDBY POWER DISSIPATION 50 uW/BIT

DTL AND TTL COMPATIBLE

@ CHIP SELECT AND OUTPUT WIRED-OR CAPABILITY FOR EASY EXPANSION

@ STANDARD 16-PIN DIP SILICONE PACKAGE

@ SIGNETICS P-MOS SILICON GATE PROCESS TECHNOLOGY

® Vcc = t5V, Vop = -7, Vp = -10V RECOMMENDED

® Vpp AND Vp MAY BE TIED FOR SINGLE NEGATIVE POWER SUPPLY (-9V RECOMMENDED)

@ GUARANTEED OPERATION WITH 3V Vpp-Vp SEPARATION

APPLICATIONS

SMALL BUFFER STORES SMALL CORE MEMORY REPLACEMENT BIPOLAR COMPATIBLE DATA STORAGE

SILICONE PACKAGING

Low cost silicone DIP packaging is implemented and reli- ability is assured by the use of Signetics unique silicon gate MOS process technology. Unlike the standard metal gate MOS process the silicon material over the gate oxide passi- vates the MOS transistors, and the deposited dielectric material over the silicon gate-oxide-substrate structure pro- vides an ion barrier. In addition, Signetics proprietary sur- face passivation and silicone packaging techniques result in an MOS circuit with inherent high reliability and demon- strating superior moisture resistance, mechanical shock and ionic contamination barriers.

PROCESS TECHNOLOGY

The use of Signetics’ unique Silicon Gate Low Threshold Process allows the design and production of higher per- formance MOS circuits and provides higher functional density on a chip than other MOS technologies.

23

SILICON GATE MOS 2500 SERIES

BIPOLAR COMPATIBILITY

All inputs of the 2501 can be driven directly by standard bipolar integrated circuits (TTL, DTL, etc.). The data out- put buffers are capable of sinking a minimum of 2.0 mA, sufficient to drive one standard TTL load.

POWER DISSIPATION

The maximum power dissipation of 1.6mW/bit is required only during Read or Write. For standby operation, 50uW/bit is obtained by removing Vp and reducing Vpp to —2.0V. Removal of Vp alone will cut power dissipation by a factor of 1.5.

SPECIAL FEATURE

The outputs of the 2501 are effectively open circuited when the device is not selected (logic 1 on chip select). This fea- ture allows OR-Tying for memory expansion,

PART IDENTIFICATION TABLE

TYPE | PACKAGE __| OP.TEMP.RANGE | 25018 | 16-pin Silicone DIP 0°C. to+70°C.

PIN CONFIGURATION (Top View)

B PACKAGE

. Address 6 . Address 8 . R/W

. Address 7 . Data Out Vo . Data Out Vec . Datatn

. Address 5 . Address 4 . Address 1 . Address 2 Vop . Address 3

. Chip Select

1 2 3 4. 5. 6 7 8.

SIGNETICS SILICON GATE MOS 2501

MAXIMUM GUARANTEED RATINGS (1)

Operating Temperature O°C to +70°C Storage Temperature -65°C to +150°C All Input or Output Voltages with

Respect to the Most Positive Supply

Voltage, Vcc +0.3V to -20V Supply Voltages Vpp and Vp with

Respect to Vcc -18V Power Dissipation at Ta = 70°C 640mW

NOTES: 1. Stresses above those listed under ‘‘Maximum Guaranteed Rating’ may cause permanent damage to the device. This is a stress rating

DC CHARACTERISTICS (Tp = 0°C to 70°C, Veg = +5V (8) , Vpp = -7+ 5%

Input Load Current

(Ail Input Pins) Output Leakage Current Power Supply Current, Vpp

Power Supply Current, Vp Power Supply Current, Vpp

Power Supply Current, Vp

»Vp =-10V+ 5% unless otherwise specified.

24

only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.

. For operating at elevated temperatures the device must be .

derated based on a +150°C maximum junction temperature and a thermal resistance of 150°C/W junction to ambient.

. All inputs are protected against static charge. . Parameters are valid over operating temperature range unless

specified.

. All voltage measurements are referenced to ground. . Manufacturer reserves the right to make design and process

changes and improvements.

_ Typical vatues are at +25°C and nominal supply voltages. A Vec tolerance is +5%. Any variation in actual Vec will be

tracked directly by V; Lo Vin and Vou which are stated for a Vec of exactly 5 volts.

See notes above)

CONDITIONS

VIN = 0.0V; Ta = +25 C

VOUT = 0.0V, Chip Select Input = +3.3V, Tp, = +25°C

lo, =0.0mMA Ta, = +25°C Vpp = Vp =-9V

SIGNETICS SILICON GATE MOS 2501

SWITCHING CHARACTERISTICS Guaranteed Limits Ta =+25°C , Voc = +5V (8) , Vpp = -7V4.5% , Vp = -10V+5% except as noted.

READ CYCLE WRITE CYCLE

SYMBOL TEST LIMITS (usec) MAX SYMBOL TEST LIMITS (usec) MIN. [Resa

BLOCK DIAGRAM

PULSE GENERATOR

256-BIT RAM PLANE

X ADDRESS DECODE X LINE DRIVERS

DATA PULSE MODEL 203 DATA GEN. CH2 OuT

EXT. —ND cock §=P stock

NOTES:

1. Each clock time is split into a Read followed by a Write. Read and Write times can be varied by adjustment of the “‘delay’”’ and DATAINIZO “width’' controls of the pulse generator.

. Data generator produces a 256-bit block of data, 32 bits repeated 8 times. ‘‘PCM’’ mode used so data can be changed in 32 bits of the 2501 from one cycle to the next.

3. All inputs to the 2501 are standard TTL outputs with Vec = +5V +5%.

. Access time is measured between A1 (least significant address input) and points 1 and 2.

5. Vpop =Vpb = —-9V

CONDITIONS OF TEST

Input pulse amplitudes: 0 to +5V, Input pulse rise and fall times: < 10 nsec. Speed measurements referenced to